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Signal Name
Dir.
Pin
Description
This signal is a DMA Request that is used for DMA data
transfers between host and device. It shall be asserted by the
device when it is ready to transfer data to or from the host. For
Multiword DMA transfers, the direction of data transfer is
controlled by – IORD and – IOWR. This signal is used in a
handshake manner with – DMACK, i.e., the device shall wait
until the host asserts – DMACK before negating DMARQ, and
reasserting DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
DMARQ
(True IDE Mode)
– IORD
(PC Card Memory Mode)
– IORD
(PC Card I/O Mode)
– IORD
(True IDE Mode)
While a DMA operation is in progress, -CS0 and – CS1 shall be
held negated and the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this
output signal is not used and should not be connected at the
host. In this case, the BIOS must report that DMA mode is not
supported by the host so that device drivers will not attempt
DMA mode.
A host that does not support DMA mode and implements both
PCMCIA and True-IDE modes of operation need not alter the
PCMCIA mode connections while in True-IDE mode as long as
this does not prevent proper operation in any mode.
This signal is not used in this mode.
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the CompactFlash Storage
Card when the card is configured to use the I/O
interface.
In True IDE Mode, while Ultra DMA mode is not active, this
signal has the same function as in PC Card I/O Mode.
-HDMARDY
(True IDE Mode – In Ultra
DMA Protocol DMA
Read)
I
34
In True IDE Mode when Ultra DMA mode DMA Read is active,
this signal is asserted by the host to indicate that the host is
read
to receive Ultra DMA data-in bursts. The host may negate
-HDMARDY to pause an Ultra DMA transfer.
In True IDE Mode when Ultra DMA mode DMA Write is active,
HSTROBE
(True IDE Mode – In Ultra
DMA Protocol DMA
Write)
– CD1, – CD2
(PC Card Memory Mode)
this signal is the data out strobe generated by the host. Both
the
rising and falling edge of HSTROBE cause data to be latched by
the device. The host may stop generating HSTROBE edges to
pause an Ultra DMA data-out burst.
These Card Detect pins are connected to ground on the
CompactFlash Storage Card. They are used by the
host to determine that the CompactFlash Storage Card or is fully
– CD1, – CD2
(PC Card I/O Mode)
– CD1, – CD2
(True IDE Mode)
O
26, 25
inserted into its socket.
This signal is the same for all modes.
This signal is the same for all modes.
These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is being
performed. – CE2 always accesses the odd byte of the word.
– CE1, – CE2
(PC Card Memory Mode)
-CE1 accesses the even byte or the Odd byte of the word
depending on A0 and – CE2. A multiplexing scheme based on
A0,
-CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See
– CE1, – CE2
(PC Card I/O Mode)
– CS0, – CS1
(True IDE Mode)
I
7, 32
Table 31 , Table 39 , Table 40Table 41 , and Table 42 .
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, -CS0 is the chip select for the task file
registers while – CS1 is used to select the Alternate Status
Register and the Device Control Register.
While – DMACK is asserted, -CS0 and – CS1 shall be held
negated and the width of the transfers shall be 16 bits.
– CSEL
(PC Card Memory Mode)
I
39
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.51
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-300_data_sheet_CF-HxBK_Rev151.doc
Page 16 of 99
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